Chip Testing & Burn-in

Bigger dies, more chiplets and HBM stacks multiply test time. SoC and memory testers become a quiet throughput gate for every accelerator shipped.

Wafer probe→Final test→Burn-in→Ship

Tightness score ⓘ

#22 of 56

▲ Tightening

Supply concentration4

Lead time3

Capex intensity3

Geopolitical exposure3

Pricing power4

Lead time

6–12 mo

Theme 1M

−22.5%

% in uptrend

Metric to watch

Advantest and Teradyne SoC-test orders, test time per device, and burn-in commentary.

What would prove us wrong

Weakens if tester lead times shorten while accelerator unit volumes rise.

Dependencies

Equal-weight · rebased 100 · 1Y

Stocks we track

Who controls this bottleneck

Roles, not recommendations. Delayed prices; local currency.

Stock	Role	Listing	Last	1D	1M	3M	YTD	Off 52w high	Next earnings
6857.T Advantest	SoC and memory testers for AI accelerators and HBM	TSE Japan	¥29,985	−4.63%	−25.8%	−6.7%	+53.1%	−28.4%	2027-01-27
TER Teradyne	SoC test plus Universal Robots cobots	NASDAQ US	$263.8	−0.76%	−26.6%	−37.0%	+36.4%	−45.5%	2027-01-27
FORM FormFactor	Probe cards incl. HBM wafer probe	NASDAQ US	$92.32	−3.61%	−22.9%	−29.9%	+65.5%	−42.3%	2026-10-28
AEHR Aehr Test Systems	Wafer-level burn-in	NASDAQ US	$61.04	−7.21%	−14.6%	−54.5%	+202.3%	−58.1%	2026-11-02
COHU Cohu	Test handlers and interface	NASDAQ US	$45.00	−2.13%	−22.7%	−24.1%	+93.4%	−39.1%	2026-10-28

Auto-updated